Index | index by Group | index by Distribution | index by Vendor | index by creation date | index by Name | Mirrors | Help | Search |
Name: microcode_ctl | Distribution: CentOS |
Version: 20240531 | Vendor: CentOS |
Release: 1.el10 | Build date: Mon Jul 29 20:17:41 2024 |
Group: Unspecified | Build host: x86-01.stream.rdu2.redhat.com |
Size: 13239579 | Source RPM: microcode_ctl-20240531-1.el10.src.rpm |
Packager: builder@centos.org | |
Url: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files | |
Summary: CPU microcode updates for Intel x86 processors |
This package provides microcode update files for Intel x86 and x86_64 CPUs. The microcode update is volatile and needs to be uploaded on each system boot i.e. it isn't stored on a CPU permanently; reboot and it reverts back to the old microcode. Package name "microcode_ctl" is historical, as the binary with the same name is no longer used for microcode upload and, as a result, no longer provided.
CC0 and Redistributable, no modification permitted
* Fri Jul 26 2024 Eugene Syromiatnikov <esyr@redhat.com> - 4:20240531-1 - Bring in RHEL-specific packaging bits. * Mon Jun 24 2024 Troy Dawson <tdawson@redhat.com> - 2:2.1-62 - Bump release for June 2024 mass rebuild * Thu Jan 25 2024 Fedora Release Engineering <releng@fedoraproject.org> - 2:2.1-61 - Rebuilt for https://fedoraproject.org/wiki/Fedora_40_Mass_Rebuild * Sun Jan 21 2024 Fedora Release Engineering <releng@fedoraproject.org> - 2:2.1-60 - Rebuilt for https://fedoraproject.org/wiki/Fedora_40_Mass_Rebuild * Wed Jan 10 2024 Eugene Syromiatnikov <esyr@redhat.com> 2:2.1-59 - migrated to SPDX license * Tue Nov 14 2023 Eugene Syromiatnikov <esyr@redhat.com> 2:2.1-58 - Update to upstream 2.1-42. 20231114 - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd0003a5 up to 0xd0003b9; - Update of 06-6c-01/0x10 (ICL-D B0) microcode from revision 0x1000230 up to 0x1000268; - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xbc up to 0xc2; - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode from revision 0xac up to 0xb4; - Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x2c up to 0x34; - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x46 up to 0x4e; - Update of 06-8f-04/0x10 microcode from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-04) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-04) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-04) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-05) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-05) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-06) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-06/0x10 microcode from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-06) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-08) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision 0x2e up to 0x32; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-97-02) from revision 0x2e up to 0x32; - Update of 06-bf-02/0x07 (RPL-S 8+8 C0) microcode (in intel-ucode/06-97-02) from revision 0x2e up to 0x32; - Update of 06-bf-05/0x07 (RPL-S 6+0 C0) microcode (in intel-ucode/06-97-02) from revision 0x2e up to 0x32; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-97-05) from revision 0x2e up to 0x32; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x2e up to 0x32; - Update of 06-bf-02/0x07 (RPL-S 8+8 C0) microcode (in intel-ucode/06-97-05) from revision 0x2e up to 0x32; - Update of 06-bf-05/0x07 (RPL-S 6+0 C0) microcode (in intel-ucode/06-97-05) from revision 0x2e up to 0x32; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision 0x42c up to 0x430; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in intel-ucode/06-9a-03) from revision 0x42c up to 0x430; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in intel-ucode/06-9a-04) from revision 0x42c up to 0x430; - Update of 06-9a-04/0x40 (AZB A0) microcode from revision 0x4 up to 0x5; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x42c up to 0x430; - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x59 up to 0x5d; - Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x119 up to 0x11d; - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision 0x4119 up to 0x411c; - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in intel-ucode/06-ba-02) from revision 0x4119 up to 0x411c; - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in intel-ucode/06-ba-03) from revision 0x4119 up to 0x411c; - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4119 up to 0x411c; - Update of 06-be-00/0x11 (ADL-N A0) microcode from revision 0x11 up to 0x12; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-02) from revision 0x2e up to 0x32; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-02) from revision 0x2e up to 0x32; - Update of 06-bf-02/0x07 (RPL-S 8+8 C0) microcode from revision 0x2e up to 0x32; - Update of 06-bf-05/0x07 (RPL-S 6+0 C0) microcode (in intel-ucode/06-bf-02) from revision 0x2e up to 0x32; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-05) from revision 0x2e up to 0x32; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-05) from revision 0x2e up to 0x32; - Update of 06-bf-02/0x07 (RPL-S 8+8 C0) microcode (in intel-ucode/06-bf-05) from revision 0x2e up to 0x32; - Update of 06-bf-05/0x07 (RPL-S 6+0 C0) microcode from revision 0x2e up to 0x32. - Addresses CVE-2023-23583 * Thu Aug 10 2023 Eugene Syromiatnikov <esyr@redhat.com> 2:2.1-57 - Update to upstream 2.1-41. 20230808 - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000171 up to 0x1000181; - Update of 06-55-04/0xb7 (SKX-D/SP/W/X H0/M0/M1/U0) microcode from revision 0x2006f05 up to 0x2007006; - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4003501 up to 0x4003604; - Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision 0x5003501 up to 0x5003604; - Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002601 up to 0x7002703; - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000390 up to 0xd0003a5; - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xba up to 0xbc; - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode from revision 0xaa up to 0xac; - Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x2a up to 0x2c; - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x44 up to 0x46; - Update of 06-8e-09/0xc0 (KBL-U/U 2+3e/Y H0/J1) microcode from revision 0xf2 up to 0xf4; - Update of 06-8e-09/0x10 (AML-Y 2+2 H0) microcode from revision 0xf2 up to 0xf4; - Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0, KBL-R Y0) microcode from revision 0xf2 up to 0xf4; - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xf2 up to 0xf4; - Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0) microcode from revision 0xf6 up to 0xf8; - Update of 06-8f-04/0x10 microcode from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-04) from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-04) from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-04) from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-05) from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-05) from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-06) from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-06/0x10 microcode from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-06) from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-08) from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode from revision 0x2c0001d1 up to 0x2c000271; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision 0x2b000461 up to 0x2b0004b1; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision 0x2c up to 0x2e; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-97-02) from revision 0x2c up to 0x2e; - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x2c up to 0x2e; - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x2c up to 0x2e; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-97-05) from revision 0x2c up to 0x2e; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x2c up to 0x2e; - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x2c up to 0x2e; - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x2c up to 0x2e; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision 0x42a up to 0x42c; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in intel-ucode/06-9a-03) from revision 0x42a up to 0x42c; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in intel-ucode/06-9a-04) from revision 0x42a up to 0x42c; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x42a up to 0x42c; - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision 0xf2 up to 0xf4; - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode from revision 0xf2 up to 0xf4; - Update of 06-9e-0b/0x02 (CFL-E/H/S B0) microcode from revision 0xf2 up to 0xf4; - Update of 06-9e-0c/0x22 (CFL-H/S/Xeon E P0) microcode from revision 0xf2 up to 0xf4; - Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode from revision 0xf8 up to 0xfa; - Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xf6 up to 0xf8; - Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xf6 up to 0xf8; - Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xf6 up to 0xf8; - Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xf6 up to 0xf8; - Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision 0xf6 up to 0xf8; - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x58 up to 0x59; - Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x113 up to 0x119; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-02) from revision 0x2c up to 0x2e; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-02) from revision 0x2c up to 0x2e; - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x2c up to 0x2e; - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02) from revision 0x2c up to 0x2e; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-05) from revision 0x2c up to 0x2e; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-05) from revision 0x2c up to 0x2e; - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05) from revision 0x2c up to 0x2e; - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x2c up to 0x2e; - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision 0x4112 up to 0x4119 (old pf 0xc0); - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in intel-ucode/06-ba-02) from revision 0x4112 up to 0x4119 (old pf 0xc0); - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in intel-ucode/06-ba-03) from revision 0x4112 up to 0x4119 (old pf 0xc0); - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4112 up to 0x4119 (old pf 0xc0); - Update of 06-be-00/0x11 (ADL-N A0) microcode from revision 0x10 up to 0x11 (old pf 0x1). - Addresses CVE-2022-21216, CVE-2022-40982, CVE-2022-41804, CVE-2023-23908 * Thu Jul 20 2023 Fedora Release Engineering <releng@fedoraproject.org> - 2:2.1-56 - Rebuilt for https://fedoraproject.org/wiki/Fedora_39_Mass_Rebuild * Thu May 25 2023 Eugene Syromiatnikov <esyr@redhat.com> 2:2.1-55 - Update to upstream 2.1-40. 20230516 - Addition of 06-6c-01/0x10 (ICL-D B0) microcode at revision 0x1000230; - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode at revision 0x2b000461; - Addition of 06-8f-04/0x10 microcode at revision 0x2c0001d1; - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-04) at revision 0x2b000461; - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-04) at revision 0x2c0001d1; - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-04) at revision 0x2b000461; - Addition of 06-8f-06/0x10 (SPR-HBM B2) microcode (in intel-ucode/06-8f-04) at revision 0x2c0001d1; - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-04) at revision 0x2b000461; - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-04) at revision 0x2b000461; - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-04) at revision 0x2c0001d1; - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-05) at revision 0x2b000461; - Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) at revision 0x2c0001d1; - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode at revision 0x2b000461; - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode at revision 0x2c0001d1; - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-05) at revision 0x2b000461; - Addition of 06-8f-06/0x10 (SPR-HBM B2) microcode (in intel-ucode/06-8f-05) at revision 0x2c0001d1; - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-05) at revision 0x2b000461; - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-05) at revision 0x2b000461; - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-05) at revision 0x2c0001d1; - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-06) at revision 0x2b000461; - Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) at revision 0x2c0001d1; - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-06) at revision 0x2b000461; - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-06) at revision 0x2c0001d1; - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode at revision 0x2b000461; - Addition of 06-8f-06/0x10 (SPR-HBM B2) microcode at revision 0x2c0001d1; - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-06) at revision 0x2b000461; - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-06) at revision 0x2b000461; - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-06) at revision 0x2c0001d1; - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-07) at revision 0x2b000461; - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-07) at revision 0x2b000461; - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-07) at revision 0x2b000461; - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode at revision 0x2b000461; - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-07) at revision 0x2b000461; - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-08) at revision 0x2b000461; - Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) at revision 0x2c0001d1; - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-08) at revision 0x2b000461; - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-08) at revision 0x2c0001d1; - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-08) at revision 0x2b000461; - Addition of 06-8f-06/0x10 (SPR-HBM B2) microcode (in intel-ucode/06-8f-08) at revision 0x2c0001d1; - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-08) at revision 0x2b000461; - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode at revision 0x2b000461; - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode at revision 0x2c0001d1; - Addition of 06-b7-01/0x32 (RPL-S S0) microcode at revision 0x113; - Addition of 06-ba-02/0xc0 (RPL-H 6+8/P 6+8 J0) microcode at revision 0x4112; - Addition of 06-ba-03/0xc0 (RPL-U 2+8 Q0) microcode (in intel-ucode/06-ba-02) at revision 0x4112; - Addition of 06-ba-02/0xc0 (RPL-H 6+8/P 6+8 J0) microcode (in intel-ucode/06-ba-03) at revision 0x4112; - Addition of 06-ba-03/0xc0 (RPL-U 2+8 Q0) microcode at revision 0x4112; - Addition of 06-be-00/0x01 (ADL-N A0) microcode at revision 0x10; - Addition of 06-9a-04/0x40 (AZB A0/R0) microcode at revision 0x4; - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x100015e up to 0x1000171; - Update of 06-55-04/0xb7 (SKX-D/SP/W/X H0/M0/M1/U0) microcode from revision 0x2006e05 up to 0x2006f05; - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4003302 up to 0x4003501; - Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision 0x5003302 up to 0x5003501; - Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002501 up to 0x7002601; - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000375 up to 0xd000390; - Update of 06-7a-01/0x01 (GLK B0) microcode from revision 0x3c up to 0x3e; - Update of 06-7a-08/0x01 (GLK-R R0) microcode from revision 0x20 up to 0x22; - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xb2 up to 0xba; - Update of 06-8a-01/0x10 (LKF B2/B3) microcode from revision 0x31 up to 0x33; - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode from revision 0xa4 up to 0xaa; - Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x28 up to 0x2a; - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x40 up to 0x44; - Update of 06-8e-09/0x10 (AML-Y 2+2 H0) microcode from revision 0xf0 up to 0xf2; - Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0, KBL-R Y0) microcode from revision 0xf0 up to 0xf2; - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xf0 up to 0xf2; - Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0) microcode from revision 0xf0 up to 0xf6; - Update of 06-96-01/0x01 (EHL B1) microcode from revision 0x16 up to 0x17; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision 0x421 up to 0x42a; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in intel-ucode/06-9a-03) from revision 0x421 up to 0x42a; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in intel-ucode/06-9a-04) from revision 0x421 up to 0x42a; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x421 up to 0x42a; - Update of 06-9c-00/0x01 (JSL A0/A1) microcode from revision 0x24000023 up to 0x24000024; - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision 0xf0 up to 0xf2; - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode from revision 0xf0 up to 0xf2; - Update of 06-9e-0b/0x02 (CFL-E/H/S B0) microcode from revision 0xf0 up to 0xf2; - Update of 06-9e-0c/0x22 (CFL-H/S/Xeon E P0) microcode from revision 0xf0 up to 0xf2; - Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode from revision 0xf0 up to 0xf8; - Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xf0 up to 0xf6; - Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xf0 up to 0xf6; - Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xf0 up to 0xf6; - Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xf0 up to 0xf6; - Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision 0xf0 up to 0xf6; - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x54 up to 0x58; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-97-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-97-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x22 up to 0x2c (old pf 0x3). - Addresses CVE-2022-21216, CVE-2022-33196, CVE-2022-33972, CVE-2022-38090 * Thu Jan 19 2023 Fedora Release Engineering <releng@fedoraproject.org> - 2:2.1-54 - Rebuilt for https://fedoraproject.org/wiki/Fedora_38_Mass_Rebuild * Tue Aug 09 2022 Eugene Syromiatnikov <esyr@redhat.com> 2:2.1-53 - Update to upstream 2.1-37. 20220809 - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x100015d up to 0x100015e; - Update of 06-55-04/0xb7 (SKX-D/SP/W/X H0/M0/M1/U0) microcode from revision 0x2006d05 up to 0x2006e05; - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000363 up to 0xd000375; - Update of 06-7a-01/0x01 (GLK B0) microcode from revision 0x3a up to 0x3c; - Update of 06-7a-08/0x01 (GLK-R R0) microcode from revision 0x1e up to 0x20; - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xb0 up to 0xb2; - Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x26 up to 0x28; - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x3e up to 0x40; - Update of 06-97-02/0x03 (ADL-HX/S 8+8 C0) microcode from revision 0x1f up to 0x22; - Update of 06-97-05/0x03 (ADL-S 6+0 K0) microcode (in intel-ucode/06-97-02) from revision 0x1f up to 0x22; - Update of 06-bf-02/0x03 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x1f up to 0x22; - Update of 06-bf-05/0x03 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x1f up to 0x22; - Update of 06-97-02/0x03 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-97-05) from revision 0x1f up to 0x22; - Update of 06-97-05/0x03 (ADL-S 6+0 K0) microcode from revision 0x1f up to 0x22; - Update of 06-bf-02/0x03 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x1f up to 0x22; - Update of 06-bf-05/0x03 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x1f up to 0x22; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision 0x41c up to 0x421; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in intel-ucode/06-9a-03) from revision 0x41c up to 0x421; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in intel-ucode/06-9a-04) from revision 0x41c up to 0x421; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x41c up to 0x421; - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x53 up to 0x54; - Update of 06-97-02/0x03 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-02) from revision 0x1f up to 0x22; - Update of 06-97-05/0x03 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-02) from revision 0x1f up to 0x22; - Update of 06-bf-02/0x03 (ADL C0) microcode from revision 0x1f up to 0x22; - Update of 06-bf-05/0x03 (ADL C0) microcode (in intel-ucode/06-bf-02) from revision 0x1f up to 0x22; - Update of 06-97-02/0x03 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-05) from revision 0x1f up to 0x22; - Update of 06-97-05/0x03 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-05) from revision 0x1f up to 0x22; - Update of 06-bf-02/0x03 (ADL C0) microcode (in intel-ucode/06-bf-05) from revision 0x1f up to 0x22; - Update of 06-bf-05/0x03 (ADL C0) microcode from revision 0x1f up to 0x22. - Addresses CVE-2022-21233
/etc/microcode_ctl /etc/microcode_ctl/ucode_with_caveats /lib/firmware/intel-ucode /usr/lib/dracut/dracut.conf.d/01-microcode.conf /usr/lib/dracut/dracut.conf.d/99-microcode-override.conf /usr/lib/dracut/modules.d/99microcode_ctl-fw_dir_override /usr/lib/dracut/modules.d/99microcode_ctl-fw_dir_override/module-setup.sh /usr/lib/systemd/system/microcode.service /usr/libexec/microcode_ctl /usr/libexec/microcode_ctl/check_caveats /usr/libexec/microcode_ctl/reload_microcode /usr/libexec/microcode_ctl/update_ucode /usr/share/doc/microcode_ctl /usr/share/doc/microcode_ctl/LICENSE.intel-ucode /usr/share/doc/microcode_ctl/README /usr/share/doc/microcode_ctl/README.caveats /usr/share/doc/microcode_ctl/README.intel-ucode /usr/share/doc/microcode_ctl/RELEASE_NOTES.intel-ucode /usr/share/doc/microcode_ctl/SECURITY.intel-ucode /usr/share/doc/microcode_ctl/SUMMARY.intel-ucode /usr/share/doc/microcode_ctl/caveats /usr/share/doc/microcode_ctl/caveats/06-4f-01_readme /usr/share/doc/microcode_ctl/caveats/intel_readme /usr/share/microcode_ctl /usr/share/microcode_ctl/intel-ucode /usr/share/microcode_ctl/ucode_with_caveats /usr/share/microcode_ctl/ucode_with_caveats/intel /usr/share/microcode_ctl/ucode_with_caveats/intel-06-4f-01 /usr/share/microcode_ctl/ucode_with_caveats/intel-06-4f-01/config /usr/share/microcode_ctl/ucode_with_caveats/intel-06-4f-01/disclaimer /usr/share/microcode_ctl/ucode_with_caveats/intel-06-4f-01/intel-ucode /usr/share/microcode_ctl/ucode_with_caveats/intel-06-4f-01/intel-ucode/06-4f-01 /usr/share/microcode_ctl/ucode_with_caveats/intel-06-4f-01/readme /usr/share/microcode_ctl/ucode_with_caveats/intel/config /usr/share/microcode_ctl/ucode_with_caveats/intel/disclaimer /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-03-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-05-00 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-05-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-05-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-05-03 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-06-00 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-06-05 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-06-0a /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-06-0d /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-07-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-07-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-07-03 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-08-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-08-03 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-08-06 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-08-0a /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-09-05 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-0a-00 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-0a-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-0b-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-0b-04 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-0d-06 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-0e-08 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-0e-0c /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-0f-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-0f-06 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-0f-07 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-0f-0a /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-0f-0b /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-0f-0d /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-16-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-17-06 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-17-07 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-17-0a /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-1a-04 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-1a-05 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-1c-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-1c-0a /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-1d-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-1e-05 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-25-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-25-05 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-26-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-2a-07 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-2c-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-2d-06 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-2d-07 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-2e-06 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-2f-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-37-08 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-37-09 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-3a-09 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-3c-03 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-3d-04 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-3e-04 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-3e-06 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-3e-07 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-3f-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-3f-04 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-45-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-46-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-47-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-4c-03 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-4c-04 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-4d-08 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-4e-03 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-55-03 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-55-04 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-55-05 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-55-06 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-55-07 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-55-0b /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-56-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-56-03 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-56-04 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-56-05 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-5c-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-5c-09 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-5c-0a /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-5e-03 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-5f-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-66-03 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-6a-05 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-6a-06 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-6c-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-7a-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-7a-08 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-7e-05 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-8a-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-8c-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-8c-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-8d-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-8e-09 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-8e-0a /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-8e-0b /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-8e-0c /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-8f-05 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-8f-06 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-8f-07 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-8f-08 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-96-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-97-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-97-05 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-9a-03 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-9a-04 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-9c-00 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-9e-09 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-9e-0a /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-9e-0b /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-9e-0c /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-9e-0d /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-a5-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-a5-03 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-a5-05 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-a6-00 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-a6-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-a7-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-aa-04 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-b7-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-ba-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-ba-03 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-ba-08 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-be-00 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-bf-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-bf-05 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-cf-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/06-cf-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-00-07 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-00-0a /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-01-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-02-04 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-02-05 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-02-06 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-02-07 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-02-09 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-03-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-03-03 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-03-04 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-04-01 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-04-03 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-04-04 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-04-07 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-04-08 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-04-09 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-04-0a /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-06-02 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-06-04 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-06-05 /usr/share/microcode_ctl/ucode_with_caveats/intel/intel-ucode/0f-06-08 /usr/share/microcode_ctl/ucode_with_caveats/intel/readme
Generated by rpm2html 1.8.1
Fabrice Bellet, Wed Nov 27 07:34:16 2024